(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a ring shaped, or a cylindrical shaped, storage node structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, such as DRAM memory devices The DRAM device is usually comprised of a transfer gate transistor, and a capacitor structure, such as an overlying stacked capacitor structure. The signal, or performance of the DRAM device, is dependent on the magnitude of capacitance supplied by the stacked capacitor structure. The capacitance of the stacked structure can be increased via increases in the surface area of the storage node component of the capacitor, however the horizontal dimension of the overlying stacked capacitor structure is limited by the horizontal dimension of the underlying transfer gate transistor, and since another objective of the semiconductor industry is to decrease the size of the semiconductor chip, increasing the horizontal dimension of a transfer gate transistor, and of an overlying stacked capacitor structure, is not a viable option.
A method used to increase storage node area, without increasing the horizontal dimension of this structure, has been the use of crown shaped, storage node structures, such as a polysilicon crown shaped storage node structure, comprised of multiple vertical polysilicon features, and comprised of a horizontal polysilicon feature, with the horizontal polysilicon feature overlying, and contacting, an underlying storage node plug, and connecting the multiple, vertical polysilicon features. However the fabrication process used for crown shaped storage node structures, such as the structures described by Yang et al, in U.S. Pat. No. 5,804,852, can present process complexity, and increased cost. For example the exposed surfaces of a capacitor opening, in an insulator layer, are coated with a polysilicon layer, that the crown shaped storage node structure will be formed from. One method of defining the desired crown shaped storage node structure is the use of a chemical mechanical polishing. (CMP), procedure, employed to remove the region of the polysilicon layer, located on the top surface of the insulator layer, in which the capacitor opening is formed in, resulting in the crown shaped storage node structure, in the capacitor opening. However this method can result in particles from a CMP slurry, locating on the horizontal polysilicon feature, at the bottom of the capacitor opening, interfering with the subsequent formation of a capacitor dielectric layer, on the surface of the crown shaped storage node structure. The capacitor opening can be protected, or filled by a photoresist plug, however the additional cost of forming the photoresist plug, in the capacitor opening, in addition to the process needed to remove CMP slurry particles, from the top of the photoresist plug, adds complexity to an already complex and costly process.
This invention will describe a process for forming a cylindrical shaped, storage node structure, for a DRAM capacitor, without the use of a storage node defining, CMP procedure, thus avoiding the cost, and complexity, of storage node patterning sequences that employ a CMP procedure, and photoresist plugs. This invention will feature a polysilicon layer, coating, or lining, the exposed surfaces of a capacitor opening, however followed by a blanket, anisotropic, reactive ion etching, (RIE), procedure, used to remove regions of the polysilicon layer that reside on the top surface of the insulator layer, in which the capacitor opening was formed in, as well removing the region of polysilicon residing at the bottom of the capacitor opening, The capacitor opening was formed, exposing the underlying storage node plug structure, at the edge, or perimeter, of the capacitor opening, thus allowing an edge, or segment, of the cylindrical shaped, polysilicon storage node structure, to contact a portion of the top surface of the underlying storage node plug structure. Since contact between the cylindrical shaped storage node structure, and the underlying storage node plug structure, occurs at the edge of the capacitor opening, the connecting, horizontal polysilicon feature, is not needed, thus eliminating the need for a costly CMP procedure, and a complex process sequence, needed for the post-CMP cleans.